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asahi kasei [AK4556] ms0559-e-00 2006/11 - 1 - general description the AK4556 is a low voltage 24bit 192khz codec for high performance battery powered digital audio subsystems. the dynamic performance to power supply voltage ratio is very high, attaining 103db and 106db snr for adc and dac, respectively. sampli ng rates up to 216khz are supported. the AK4556 reduces jitter sensitivity by using an integrated switched-capacitor filter. the analog inputs and outputs are single-ended to minimize pin count and external filtering requirements. packaged in a very small 20-pin tssop, the AK4556 is ideal for space-sensitive applications. features ? single-ended adc - dynamic range, s/n: 103db@va=3.0v - s/(n+d): 91db@va=3.0v - hpf for dc-offset cancel (fc = 1hz @ fs=48khz) - hpf can be disabled ? single-ended dac - dynamic range, s/n: 106db@va=3.0v - s/(n+d): 90db@va=3.0v - digital de-emphasis for 32khz, 44.1khz and 48khz sampling ? audio i/f format: msb first, 2?s complement - adc: 24bit msb justified or i 2 s compatible - dac: 24bit msb justified, 24bit lsb justified or i 2 s compatible ? input/output voltage: adc = 2.1vpp @ va=3.0v dac = 2.1vpp @ va=3.0v ? master/slave mode ? sampling rate: - normal speed: 8khz to 54khz (256fs or 512fs) 8khz to 48khz (384fs or 768fs) - double speed: 54khz to 108khz (256fs) 48khz to 96khz (384fs) - quad speed: 108khz to 216khz (128fs) 96khz to 192khz (192fs) ? master clock: - slave mode: 256fs, 384fs, 512fs or 768fs (normal speed) 256fs or 384fs (double speed) 128fs or 192fs (quad speed) - master mode: 256fs or 512fs (normal speed) 256fs (double speed) 128fs (quad speed) ? power supply: 2.4 to 3.6v (normal speed, double speed) 2.7 to 3.6v (quad speed) ? power supply current: 27.5ma ? ta = -40 to 85c ? very small package: 20pin tssop ? upper compatible with ak4552 3v 192khz 24bit ? codec AK4556
asahi kasei [AK4556] ms0559-e-00 2006/11 - 2 - modulator mclk va vss lout lin lrck bclk vcom rin ? modulator decimation filter serial i/o interface common voltage sdto ? decimation filter sdti cks3 clock divider rout 8x interpolator 8x interpolator ? ? pdn lpf lpf cks2 vd cks1 cks0 dem0 dem1 figure 1. block diagram ? compatibility with the ak4552 1. function function ak4552 AK4556 fs (max) 100khz 216khz hfp cut-off 3.7hz @ fs = 48khz 1hz @ fs = 48khz hpf disable no yes adc input level 0.617 x va 0.7 x va input resistance 34k ? @ fs = 44.1khz, 24k ? @ fs = 96khz 8k ? @ fs = 48khz, 96khz, 192khz init cycle 2081/fs 4134/fs @ normal speed, slave mode s/(n+d) 89db 91db dr, s/n 97db 103db sa 65db 68db sb 29.4khz 28khz df gd 17/fs 18/fs dac output level 0.583 x va 0.7 x va road resistance 10k ? 5k ? s/(n+d) 88db 90db dr, s/n 100db 106db sa 43db 54db df gd 15.4/fs 21/fs 256/384/512/768fs @ normal speed mode 256/384/512/768fs @ normal speed 256/384fs @ double speed mode 128/192fs @ double speed monitor 256/384fs @ double speed mclk (slave) 64/96/128/192fs @ quad speed monitor 128/192fs @ quad speed monitor mode yes (double / quad) no m/s mode slave master / slave adc 24bit msb justified 24bit msb justified / i 2 s audio i/f dac 24bit lsb justified 24bit msb justified /24bit lsb justified / i 2 s idd (vdd = 3v) 14ma 27.5ma vdd 2.4v to 4.0v 2.4v to 3.6v (normal/double speed) 2.7v to 3.6v (quad speed) package 16tssop (5.0mm x 6.4mm, 0.65mm pitch) 20tssop (6.5mm x 6.4mm, 0.65mm pitch)
asahi kasei [AK4556] ms0559-e-00 2006/11 - 3 - 2. pin layout 1 rin lin v a vss vd dem0 dem1 sdto top view 2 3 4 5 6 7 8 rout lout pdn bclk mclk lrck sdti 20 19 18 17 16 15 14 13 vcom cks0 csk1 9 10 cks3 csk2 12 11 ak4552 AK4556
asahi kasei [AK4556] ms0559-e-00 2006/11 - 4 - ? ordering guide AK4556vt -40 +85 c 20pin tssop (0.65mm pitch) akd4556 evaluation board for AK4556 ? pin layout 1 rin lin va vss vd dem0 dem1 sdto top view 2 3 4 5 6 7 8 rout lout pdn bclk mclk lrck sdti 20 19 18 17 16 15 14 13 vcom cks0 csk1 9 10 cks3 csk2 12 11
asahi kasei [AK4556] ms0559-e-00 2006/11 - 5 - pin/function no. pin name i/o function 1 rin i rch analog input pin 2 lin i lch analog input pin 3 vss - ground pin 4 va - analog power supply pin 5 vd - digital power supply pin 6 dem0 i de-emphasis control pin 7 dem1 i de-emphasis control pin 8 sdto o audio serial data output pin when pdn pin is ?l?, sdto pin outputs ?l?. 9 cks0 i mode setting pin #0 10 csk1 i mode setting pin #1 11 csk2 i mode setting pin #2 12 csk3 i mode setting pin #3 13 sdti i audio serial data input pin 14 lrck i/o input/output channel clock pin when pdn pin is ?l?, lrck pin outputs ?l? in master mode. 15 mclk i master clock input pin 16 bclk i/o audio serial data clock pin when pdn pin is ?l?, bclk pin outputs ?l? in master mode. 17 pdn i power-down & reset mode pin ?l?: power-down and reset, ?h?: normal operation the AK4556 should be reset once by bringing pdn pin = ?l?. 18 vcom o common voltage output pin, 0.5 x va 19 lout o lch analog output pin when pdn pin is ?l?, lout pin becomes hi-z. 20 rout o rch analog output pin when pdn pin is ?l?, rout pin becomes hi-z. note: do not allow digital input pins except analog input pins (lin and rin) to float. ? handling of unused pin the unused i/o pin should be processed appropriately as below. classification pi n name setting analog input lin, rin these pins should be open. analog output lout, rout these pins should be open.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 6 - absolute maximum ratings (vss=0v; note 1) parameter symbol min max units power supplies analog digital va vd -0.3 -0.3 4.6 4.6 v v input current (any pin except supplies) iin - 10 ma analog input voltage (lin, rin pin) vina -0.3 va+0.3 v digital input voltage (note 2) vind -0.3 vd+0.3 v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. dem1, dem0, cks3, cks2, cks1, ck s0, sdti, lrck, bclk, mclk and pdn pins warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (normal/double speed) (vss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital difference va vd vd - va 2.4 2.4 - 3.0 3.0 - 3.6 3.6 0.3 v v v recommended operating conditions (quad speed) (vss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital difference va vd vd - va 2.7 2.7 - 3.0 3.0 - 3.6 3.6 0.3 v v v note 1. all voltages with respect to ground. note 3. the power up sequence between va and vd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this data sheet.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 7 - analog characteristics (ta=25 c; va=vd=3.0v; vss=0v; fs=48khz, 96khz, 192khz; signal frequency=1khz; bclk=64fs; data=24bit measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz, 40hz 40khz at fs=192khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: resolution - - 24 bits input voltage (note 4) 1.9 2.1 2.3 vpp fs=48khz ? 1dbfs 82 91 - db bw=20khz ? 60dbfs - 40 - db fs=96khz ? 1dbfs 80 90 - db bw=40khz ? 60dbfs - 37 - db fs=192khz ? 1dbfs - 90 - db s/(n+d) bw=40khz ? 60dbfs - 37 - db dr ( ? 60dbfs with a-weighted) 95 103 - db s/n (a-weighted) 95 103 - db input resistance 6 8 - k ? interchannel isolation 90 110 - db interchannel gain mismatch - 0.1 0.5 db gain drift - 100 - ppm/ c power supply rejection (note 8) - 50 - db dac analog output characteristics: resolution - - 24 bits output voltage (note 5) 1.9 2.1 2.3 vpp fs=48khz 0dbfs 80 90 - db bw=20khz ? 60dbfs - 43 - db fs=96khz 0dbfs 78 88 - db bw=40khz ? 60dbfs - 40 - db fs=192khz 0dbfs - 88 - db s/(n+d) bw=40khz ? 60dbfs - 40 - db dr ( ? 60dbfs with a-weighted) 98 106 - db s/n (a-weighted) 98 106 - db load capacitance (note 6) - - 30 pf load resistance (note 7) 5 - - k ? interchannel isolation 90 110 - db interchannel gain mismatch - 0.1 0.5 db gain drift - 100 - ppm/ c power supply rejection (note 8) - 50 - db note 4. this value is the full scale (0db) of the input voltage. input voltage is proportional to va voltage. vin = 0.7 x va (vpp). note 5. this value is the full scale (0db) of the output voltage. output voltage is proportional to va voltage. vout = 0.7 x va (vpp). note 6. when lout/rout drives some capacitive load, a 220 ? resistor should be added in series between lout/rout and capacitive load. in this case, lout/rout pins can drive a capacitor of 400pf. note 7. for ac-load note 8. psr is applied to va and vd with 1khz, 50mvpp. vcom pin is connected to a 2.2 f electrolytic capacitor and a 0.1 f ceramic capacitor.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 8 - parameter min typ max units power supplies power supply current normal operation (pdn pin = ?h?) va - 19.5 29 ma vd fs=48khz - 8 12 ma (note 9) fs=96khz - 11 17 ma fs=192khz - 14 21 ma power down mode (pdn pin = ?l?) (note 10) va+vd - 10 100 a note 9. these values are in slave mode. in master mode, these values are 8.3ma (typ.) @ fs=48khz, 11.6ma (typ.) @ fs=96khz, 15.2ma (typ.) @ fs=192khz. note 10. all digital input pins are held vd or vss. filter characteristics (fs=48khz) (ta= -40 +85 c; va, vd=2.4 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 11) 0.1db ? 0.2db ? 3.0db pb 0 - - - 20.0 23.0 18.9 - - khz khz khz stopband (note 11) sb 28 - - khz passband ripple pr - - 0.04 db stopband attenuation sa 68 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 18 - 1/fs adc digital filter (hpf): frequency response (note 11) ? 3db ? 0.1db fr - - 1.0 6.5 - - hz hz dac digital filter (lpf): passband (note 11) 0.06db ? 6.0db pb 0 - - 24.0 21.8 - khz khz stopband (note 11) sb 26.2 - - khz passband ripple pr - 0.02 db stopband attenuation sa 54 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 21 - 1/fs dac digital filter + analog filter: frequency response (note 13) 20khz fr - -0.1 - db
asahi kasei [AK4556] ms0559-e-00 2006/11 - 9 - filter characteristics (fs=96khz) (ta= -40 +85 c; va, vd=2.4 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 11) 0.1db ? 0.2db ? 3.0db pb 0 - - - 40.0 46.0 37.8 - - khz khz khz stopband (note 11) sb 56 - - khz passband ripple pr - 0.04 db stopband attenuation sa 68 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 18 - 1/fs adc digital filter (hpf): frequency response (note 11) ? 3db ? 0.1db fr - - 2.0 13.0 - - hz hz dac digital filter (lpf): passband (note 11) 0.06db ? 6.0db pb 0 - - 48.0 43.6 - khz khz stopband (note 11) sb 52.4 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 21 - 1/fs dac digital filter + analog filter: frequency response (note 13) 40khz fr - -0.3 - db filter characteristics (fs=192khz) (ta= -40 +85 c; va, vd=2.7 3.6v; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 11) 0.1db ? 0.2db ? 3.0db pb 0 - - - 57.0 90.3 56.6 - - khz khz khz stopband (note 11) sb 112 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 70 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 18 - 1/fs adc digital filter (hpf): frequency response (note 11) ? 3db ? 0.1db fr - - 4.0 26.0 - - hz hz dac digital filter (lpf): passband (note 11) 0.5db ? 6.0db pb 0 - - 96.0 87.0 - khz khz stopband (note 11) sb 104.9 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay distortion ? gd - 0 - s group delay (note 12) gd - 21 - 1/fs dac digital filter + analog filter: frequency response (note 13) 40khz fr - -0.3 - db
asahi kasei [AK4556] ms0559-e-00 2006/11 - 10 - note 11. the passband and stopband frequencies scales with fs (sampling frequency). for example, adc: passband ( 0.1db) = 0.39375 x fs (@ fs=48khz), dac: passband ( 0.06db) = 0.45412 x fs. note 12. the calculated delay time resulting from digital filtering. for the adc, this time is from the input of an analog signal to the setting of 24bit data for both channels to the adc output register. for the dac, this time is from setting the 24 bit data both channels at the input register to the output of an analog signal. note 13. the reference frequency is 1khz. dc characteristics (ta=-40 +85 c; va, vd=2.4 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70 % vd - - - - 30 % vd v v high-level output voltage (iout=-100 a) low-level output voltage (iout=100 a) voh vol vd-0.5 - - - - 0.5 v v input leakage current iin - - 10 a
asahi kasei [AK4556] ms0559-e-00 2006/11 - 11 - switching characteristics (ta=-40 +85 c; va, vd=2.4 3.6v; c l =20pf) parameter symbol min typ max units master clock timing (mclk) frequency: 128fs, 256fs, 512fs 192fs, 384fs, 768fs pulse width low pulse width high fclk fclk tclkl tclkh 2.048 3.072 0.4/fclk 0.4/fclk - - - - 27.648 36.864 - - mhz mhz ns ns lrck (va, vd = 2.4v 3.6v) normal speed: 256fs, 512fs 384fs, 768fs fs fs 8 8 - - 54 48 khz khz frequency double speed: 256fs 384fs fs fs 54 48 - - 108 96 khz khz duty cycle slave mode master mode 45 - - 50 55 - % % lrck (va, vd = 2.7v 3.6v) frequency quad speed: 128fs 192fs fs fs 108 96 - - 216 192 khz khz duty cycle slave mode master mode 45 - - 50 55 - % % audio interface timing slave mode (va, vd = 2.4v 2.7v) bclk period: normal speed double speed bclk pulse width low pulse width high lrck edge to bclk ? ? (note 14) bclk ? ? to lrck edge (note 14) lrck to sdto (msb) (except i 2 s mode) bclk ? ? to sdto sdti hold time sdti setup time tbck tbck tbckl tbckh tlrb tblr tdlr tbsd tsdh tsds 1/128fs 1/64fs 60 60 20 20 - - 20 20 - - - - - - - - - - - - - - - - 40 40 - - ns ns ns ns ns ns ns ns ns ns slave mode (va, vd = 2.7v 3.6v) bclk period: normal speed double / quad speed bclk pulse width low pulse width high lrck edge to bclk ? ? (note 14) bclk ? ? to lrck edge (note 14) lrck to sdto (msb) (except i 2 s mode) bclk ? ? to sdto sdti hold time sdti setup time tbck tbck tbckl tbckh tlrb tblr tdlr tbsd tsdh tsds 1/128fs 1/64fs 33 33 20 20 - - 13 13 - - - - - - - - - - - - - - - - 20 20 - - ns ns ns ns ns ns ns ns ns ns note 14. bclk rising edge must not occur at the same time as lrck edge.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 12 - switching characteristics (continued) (ta=-40 +85 c; va, vd=2.4 3.6v; c l =20pf) parameter symbol min typ max units master mode (va, vd = 2.4v 2.7v) bclk frequency bclk duty bclk ? ? to lrck bclk ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds - - ? 20 ? 20 20 20 64fs 50 - - - - - - 40 40 - - hz % ns ns ns ns master mode (va, vd = 2.7v 3.6v) bclk frequency bclk duty bclk ? ? to lrck bclk ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds - - ? 20 ? 20 13 13 64fs 50 - - - - - - 20 20 - - hz % ns ns ns ns reset timing pdn pulse width (note 15) tpw 150 - - ns pdn ? ? to sdto valid (note 16) slave mode noraml speed tpwv - 4134 - 1/fs double speed tpwv - 8262 - 1/fs quad speed tpwv - 16518 - 1/fs master mode normal speed tpwv - 4131 - 1/fs double speed tpwv - 8259 - 1/fs quad speed tpwv - 16515 - 1/fs note 15. the AK4556 can be reset by bringing the pdn pin = ?l?. note 16. this cycle is the number of lrck rising edges from the pdn pin = ?h?. ? timing diagram mclk 1/fclk tclkh tclkl vih vil lrck 1/fs vih vil bclk tbck vih vil tbckh tbckl figure 2. clock timing
asahi kasei [AK4556] ms0559-e-00 2006/11 - 13 - vih vih lrck vil vih bclk tblr vil tlrb tdlr tdbs sdto vil 50%vd tsds tsdh sdti figure 3. audio data input/output timing (slave) vih lrck 50%vd bclk tlrb tdlr tbsd sdto vil 50%vd tsds tsdh sdti 50%vd figure 4. audio data input/output timing (master) pdn sdto vil tpwv tpw 50%vd figure 5. reset timing
asahi kasei [AK4556] ms0559-e-00 2006/11 - 14 - operation overview ? system clock mclk, bclk and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. mclk frequency, bclk frequency, hpf (on or off) and master/slave are selected by cks3-0 pins as shown in table 3. when mclk is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch (table 2). all external clocks (mclk, bclk and lrck) must be present unless the pdn pin = ?l?. if these clocks are not provided, the AK4556 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4556 in power-down mode (pdn pin = ?l?). in master mode, the master clock (mclk) must be provided unless the pdn pin = ?l?. mclk fs 128fs 192fs 256fs 384fs 512fs 768fs 32khz n/a n/a 8.192mhz 12.288mhz 16.384mhz 24.576mhz 44.1khz n/a n/a 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 48khz n/a n/a 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz n/a n/a 24.576mhz 36.864mhz n/a n/a 192khz 24.576mhz 36.864mhz n/a n/a n/a n/a table 1. system clock example (n/a: not available) mode sampling frequency mclk 8khz fs 54khz 256fs/512fs normal speed 8khz fs 48kkhz 384fs/768fs 54khz < fs 108khz 256fs double speed 48khz < fs 96khz 384fs 108khz < fs 216khz 128fs quad speed 96khz < fs 192khz 192fs table 2. sampling frequency range
asahi kasei [AK4556] ms0559-e-00 2006/11 - 15 - mode cks3 pin cks2 pin cks1 pin cks0 pin hpf m/s mclk audio interface format (see table 4 ) 0 (*) l l l l on slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) lj/rj 1 l l l h on slave 256/384/512/768fs (normal speed) lj/rj 2 l l h l off slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) lj/rj 3 l l h h off slave 256/384/512/768fs (normal speed) lj/rj 4 l h l l on slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) i 2 s 5 l h l h on slave 256/384/512/768fs (normal speed) i 2 s 6 l h h l off slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) i 2 s 7 l h h h off slave 256/384/512/768fs (normal speed) i 2 s 8 h l l l on slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) lj 9 h l l h on slave 256/384/512/768fs (normal speed) lj 10 h l h l off slave 128/192fs (quad speed) 256/384fs (double speed) 512/768fs (normal speed) lj 11 h l h h off slave 256/384/512/768fs (normal speed) lj 12 h h l l on master 256fs (double speed) i 2 s 13 h h l h on master 512fs (normal speed) i 2 s 14 h h h l on master 128fs (quad speed) i 2 s 15 h h h h on master 256fs (normal speed) i 2 s * ak4552 compatible mode table 3. mode setting ? audio serial interface format three modes are supported and selected by the cks3-0 pins as shown in table 3 and table 4. in all modes the serial data format is msb first, 2?s complement. the sdto is clocked out on the falling edge of bclk and the sdti is latched on the rising edge. the audio interface supports both master and slave modes. in slave mode, bclk and lrck are input. in master mode, bclk and lrck are output with the bclk frequency fixed to 64fs and the lrck frequency fixed to 1fs. also audio interface format is fixed to i 2 s mode. mode sdto sdti lrck bc lk (slave) bclk (master) lj 24bit, msb justified 24bit, msb justified h/l 48fs - i 2 s 24bit, i 2 s compatible 24bit, i 2 s compatible l/h 48fs or 32fs 64fs lj/rj 24bit, msb justified 24bit, lsb justified h/l 48fs - table 4. audio interface format
asahi kasei [AK4556] ms0559-e-00 2006/11 - 16 - lrck bclk(64fs) sdto ( o ) 0 1 2 18 19 20 21 22 0 1 2 18 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 32 10 3 2 23 figure 6. mode lj timing lrck bclk(64fs) sdto ( o ) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 32 10 3 2 figure 7. mode i 2 s timing lrck bclk(64fs) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 8. mode lj/rj timing ? de-emphasis filter the dac includes a digital de-emphasis filter (tc=50/15 s) via an integrated by iir filter. this filter corresponds to three frequencies (32khz, 44.1khz, 48khz). this setting is done by dem0 and dem1 pins. this filter is always off in double and quad speed modes. dem1 dem0 mode 0 0 44.1khz 0 1 off 1 0 48khz 1 1 32khz table 5. de-emphasis filter control
asahi kasei [AK4556] ms0559-e-00 2006/11 - 17 - ? digital high pass filter the adc has a digital high pass filter (hpf) for dc-offset cancellation. the cut-off frequency of the hpf is 1hz at fs=48khz and the frequency response at 20hz is -0.12db. it also scales with the sampling frequency (fs). the hpf is controlled by cks3-0 pins (table 3). if the hpf setting (o n/off) is changed at operating, click noise occurs by changing dc offset. ? power-down & reset the adc and dac are placed in power-down mode by bringing the pdn pin = ?l?, and each digital filter is also reset at the same time. these resets should always be done after power-up. for the adc, an analog initialization cycle starts after exiting the power-down mode. the output data, (sdto) becomes available after 4131 cycles (@ normal speed) of lrck in master mode or 4134 cycles (@ normal speed) of lrck in slave mode. during initialization, the adc digital data outputs of both channels are forced to a 2?s complement ?0?. the adc output data settles and correlates to the input signal after the end of initialization (settling time is approximately equal to the group delay time.) the initialization cycle does not affect the dac operation. idle noise the clocks may be stopped. a dc internal state pdn (1) normal operation power-down init cycle normal operation gd gd clock in mclk,lrck,bclk a dc in (analog) idle noise ?0?data a dc out (digital) normal operation power-down normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd external mute mute on gd (2) (2) (4) (3) notes: (1) slave mode (typ): 4134/fs @ normal speed, 8262/fs @ double speed, 16518/fs @ quad speed master mode (typ): 4131/fs @ normal speed, 8259/fs @ double speed, 16515/fs @ quad speed (2) click noise occurs at the ? ? of pdn signal. mute the analog output externally if the click noise influences system performance. (3) lout/rout pins become hi-z at power-down. (4) in master mode, lrck and bick output ?l? at power-down. figure 9. power-up/down sequence
asahi kasei [AK4556] ms0559-e-00 2006/11 - 18 - ? system reset the AK4556 should be reset once by bringing the pdn pin ?l? after power-up. in slave mode, reset and power down states are released by mclk and the internal timing starts clocking on the rising edge of lrck in mode lj and mode lj/rj. in mode i 2 s, it starts clocking on the falling edge of bclk after the first rising edge of bclk after the falling edge of lrck. the AK4556 is in power down state until lrck is input. in master mode, reset and power down states are released by mclk. the internal timing also starts by mclk.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 19 - system design figure 10 shows the system connection diagram. an evaluation board [akd4556] is available which demonstrates application circuit, optimum layout, power supply arrangements and measurement results. AK4556 8 7 6 3 2 1 13 14 15 16 17 18 19 20 lin va vd sdto rin sdti lrck mclk bclk pdn + 0.1u 5.1 ohm vss dem0 dem1 analog supply (3.0v) vcom lout rout 10u + 10u 0.1u mode control reset 0.1u 2.2u + 5 4 audio controller 10 9 11 12 cks1 cks2 cks3 cks0 10u 10u figure 10. system connection diagram example (mode 0: ak4552 compatible mode) notes: - vss of the AK4556 should be distributed separately from the ground external digital devices. - do not allow digital input pins to float. - when lout/rout drives some capacitive load, a 220 ? resistor should be added in series between lout/rout and capacitive load. in this case, lout/rout pins can drive capacitor of 400pf.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 20 - 1. grounding and power supply decoupling the AK4556 requires careful attention to power supply and grounding arrangements. va pin is usually supplied from analog supply in system and vd pin is supplied from va pin via 5.1 ? . alternatively if va and vd pins are supplied separately, the power up sequence is not critical. vss pin of the AK4556 should be connected to analog ground plane. system analog ground and digital ground should be connected t ogether near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4556 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the input to va voltage sets the analog input/output range. a 0.1 f ceramic capacitor and a 10 f electrolytic capacitor are connected to va and vss pins, normally. vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to these pins eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especia lly clock, should be kept away from the va, vd and vcom pins in order to avoid unwanted coupling into the AK4556. 3. analog inputs the adc inputs are single-ended and internally biased to the common voltage (50%va) with 8k ? (typ, @fs=48khz, 96khz, 192khz) resistance. the input signal range scales with the supply voltage and nominally 0.7xva vpp (typ). the adc output data format is 2?s complement. the internal hpf removes the dc offset. the AK4556 samples the analog inputs at 128fs (@ fs=48khz), 64fs (@fs=96khz) or 32fs(@192khz). the digital filter rejects noise above the stop band except for multiples of the sampling frequency of analog inputs. the AK4556 includes an anti-aliasing filter (rc filter) to attenuate a noi se around the sampling fre quency of analog inputs. 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.7 x va vpp (typ). the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). if the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. dc offsets on analog outputs are eliminated by ac coupl ing since dac outputs have dc offsets of a few mv.
asahi kasei [AK4556] ms0559-e-00 2006/11 - 21 - package 1.00 0.05 0.195 ~ 0.275 0.10 m 0.10 0.05 1.20max 6.5 0.1 0.65 4.4 0.1 20 11 10 1 0.105 ~ 0.175 0.60 0.10 6.4 0.2 0 o ~ 8 o s 0.10 s ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei akm confidential [AK4556] rev.0.4 2005/12 - 22 - marking akm 4556vt xxxxxx 1) pin #1 indication 2) date code: xxxxxx (6 digits) 3) marketing code: 4556vt revision history date (yy/mm/dd) revision reason page contents 06/11/06 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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